library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;

-- Suma Exponentes

entity sum_exp is

	port (
		p, q: in std_logic_vector(7 downto 0);
		r	: out std_logic_vector(7 downto 0);
		t	: out integer;
		z	: out std_logic
		);
end sum_exp;

architecture arch_sum_exp of sum_exp is
begin
	process (p, q)
	begin
		if (p > q) then
			r <= p;
			t <= to_integer(unsigned(p - q));
			z <= '0';
		else
			r <= q;
			t <= to_integer(unsigned(q - p));
			z <= '1';
		end if;
	end process;
end arch_sum_exp;